EDA课程设计——《数字钟》体会怎么写啊
课程设计感悟 通过这次设计，既复习了以前所学的知识，也进一步加深了对EDA的了解，让我对它有了更加浓厚的兴趣。
特别是当每一个子模块编写调试成功时，心里特别的开心。
但是在画顶层原理图时，遇到了不少问题，最大的问题就是根本没有把各个模块的VHD文件以及生成的器件都全部放在顶层文件的文件夹内，还有就是程序设计的时候考虑的不够全面，没有联系着各个模式以及实验板的情况来编写程序，以至于多考虑编写了译码电路而浪费了很多时间。
在波形仿真时，也遇到了一点困难,想要的结果不能在波形上得到正确的显示:在分频模块中，设定输入的时钟信号后，却只有二分频的结果，其余三个分频始终没反应。
后来，在数十次的调试和老师的指点之后，才发现是因为规定的信号量范围太大且信号的初始值随机，从而不能得到所要的结果。
还有的仿真图根本就不出波形，怎么调节都不管用，后来才知道原来是路径不正确，路径中不可以有汉字。
真是细节决定成败啊
总的来说，这次设计的数字钟还是比较成功的，有点小小的成就感，终于觉得平时所学的知识有了实用的价值，达到了理论与实际相结合的目的，不仅学到了不少知识，而且锻炼了自己的能力，使自己对以后的路有了更加清楚的认识，同时，对未来有了更多的信心。
EDA数字钟设计
1.Topclock（元件例化 顶层文件） Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity topclock is Port(clk,clr,en,m1,h1:in std_logic; alarm:out std_logic; secs,secg,mins,ming,hours,hourg:buffer std_logic_vector(3 downto 0)); End; 2. 秒模块程序 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity SECOND isport(clk,clr:in std_logic; sec1,sec0:out std_logic_vector(3 downto 0); co:out std_logic);end SECOND;architecture SEC of SECOND isbeginprocess(clk,clr)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clr='1' thencnt1:=0000;cnt0:=0000;elsif clk'event and clk='1' thenif cnt1=0101 and cnt0=1000 thenco<='1';cnt0:=1001;elsif cnt0<1001 thencnt0:=cnt0+1;elsecnt0:=0000;if cnt1<0101 thencnt1:=cnt1+1;elsecnt1:=0000;co<='0';end if;end if;end if;sec1<=cnt1;sec0<=cnt0;end process;end SEC;3.分模块程序 library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MINUTE isport(clk,en:in std_logic; min1,min0:out std_logic_vector(3 downto 0); co:out std_logic);end MINUTE;architecture MIN of MINUTE isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clk'event and clk='1' thenif en='1' thenif cnt1=0101 and cnt0=1000 thenco<='1';cnt0:=1001;elsif cnt0<1001 thencnt0:=cnt0+1;elsecnt0:=0000;if cnt1<0101 thencnt1:=cnt1+1;elsecnt1:=0000;co<='0';end if;end if;end if;end if;min1<=cnt1;min0<=cnt0;end process;end MIN;4.时模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity HOUR isport(clk,en:in std_logic; h1,h0:out std_logic_vector(3 downto 0));end HOUR;architecture hour_arc of HOUR isbeginprocess(clk)variable cnt1,cnt0:std_logic_vector(3 downto 0);beginif clk'event and clk='1' thenif en='1' thenif cnt1=0010 and cnt0=0011 thencnt1:=0000;cnt0:=0000;elsif cnt0<1001 thencnt0:=cnt0+1;end if;end if;end if;h1<=cnt1;h0<=cnt0;end process;end hour_arc;----5.扫描模块程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity SELTIME is port( clk:in std_logic; sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0); daout:out std_logic_vector(3 downto 0); sel:out std_logic_vector(2 downto 0));end SELTIME;architecture fun of SELTIME is signal count:std_logic_vector(2 downto 0);begin sel<=count; process(clk) begin if(clk'event and clk='1') then if(count>=101) then count<=000; else count<=count+1; end if; end if; case count is when000=>daout<= sec0; when001=>daout<= sec1; when010=>daout<= min0; when011=>daout<= min1; when100=>daout<=h0; when others =>daout<=h1; end case; end process;end fun;6.显示模块程序library ieee;use ieee.std_logic_1164.all;entity DISPLAY is port(d:in std_logic_vector(3 downto 0); q:out std_logic_vector(6 downto 0));end DISPLAY;architecture disp_are of DISPLAY isbegin process(d) begincase d is when0000 =>q<=0111111; when0001 =>q<=0000110; when0010 =>q<=1011011; when0011 =>q<=1001111; when0100 =>q<=1100110; when0101 =>q<=1101101; when0110 =>q<=1111101; when0111 =>q<=0100111; when1000 =>q<=1111111; when others =>q<=1101111;end case; end process;end disp_are;-----7.定时闹钟模块程序 library ieee;use ieee.std_logic_1164.all;entity ALERT isport(m1,m0,s1,s0:in std_logic_vector(3 downto 0); clk:in std_logic; q500,qlk:out std_logic);end ALERT;architecture sss_arc of ALERT is begin process(clk) begin if clk'event and clk='1' then if m1=0101 and m0=1001 and s1=0101 then if s0=0001 or s0=0011 or s0=0101 or s0=0111 then q500<='1'; else q500<='0'; end if; end if;if m1=0101 and m0=1001 and s1=0101 and s0=1001 thenqlk<='1';elseqlk<='0';end if;end if;end process;end sss_arc;Architecture one of topclock is Component second1 Port( clks,clr:in std_logic; secs,secg: buffer std_logic_vector(3 downto 0); cout1: out std_logic); End Component; Component min1 Port(clkm,clr:in std_logic; mins,ming:buffer std_logic_vector(3 downto 0); enmin,alarm: out std_logic); End Component; Component hour1 Port(clkh,clr:in std_logic; hours,hourg:buffer std_logic_vector(3 downto 0)); End Component; Component madapt Port(en,m1,clk,secin:in std_logic; minset:out std_logic); End Component; Component hadapt Port(en,h1,clk,minin:in std_logic; hourset:out std_logic); End Component; signal a,b,c,d: std_logic; begin u1:second1 port map(clr=>clr, secs=>secs,secg=>secg,clks=>clk, cout1=>a); u2:min1 port map(clr=>clr,alarm=>alarm, mins=>mins,ming=>ming,clkm=>b,enmin=>c); u3:hour1 port map(clr=>clr, hours=>hours,hourg=>hourg,clkh=>d); u4:madapt port map(en=>en,m1=>m1,clk=>clk,secin=>a,minset=>b); u5:hadapt port map(en=>en,h1=>h1,clk=>clk,minin=>c,hourset=>d); end;以上回答你满意么
求高手帮忙编一段EDA程序，数字钟的
\\\/\\\/以下代码只包含分和秒，如果需要小时，可自行添加module clock(clk,dig_r,seg_r); input clk; output [7:0]dig_r; output [7:0]seg_r; reg sec; reg [7:0]dig_r; reg [7:0]seg_r; reg [24:0]count; reg [15:0]hour; reg [3:0]disp_dat; always @(posedge clk) begin count=count+1'b1; if(count==25'd24000000) begin count=25'd0; sec=~sec; end end always @(negedge sec) begin hour[3:0]=hour[3:0]+1'b1; if(hour[3:0]==4'ha) begin hour[3:0]=4'h0; hour[7:4]=hour[7:4]+1'b1; if(hour[7:4]==4'h6) begin hour[7:4]=4'h0; hour[11:8]=hour[11:8]+1'b1; if(hour[11:8]==4'ha) begin hour[11:8]=4'h0; hour[15:12]=hour[15:12]+1'b1; if(hour[15:12]==4'h6) hour[15:12]=4'h0; end end end end always @(posedge clk) begin case(count[17:15]) 3'd0:disp_dat=hour[3:0]; 3'd1:disp_dat=hour[7:4]; 3'd2:disp_dat=4'ha; 3'd3:disp_dat=hour[11:8]; 3'd4:disp_dat=hour[15:12]; 3'd5:disp_dat=4'ha; 3'd6:disp_dat=8'h00; 3'd7:disp_dat=8'h00; endcase case(count[17:15]) 3'd0:dig_r=8'b11111110; 3'd1:dig_r=8'b11111101; 3'd2:dig_r=8'b11111011; 3'd3:dig_r=8'b11110111; 3'd4:dig_r=8'b11101111; 3'd5:dig_r=8'b11111111; 3'd6:dig_r=8'b11111111; 3'd7:dig_r=8'b11111111; endcase end always @(posedge clk) begin case(disp_dat) 4'h0:seg_r=8'hc0; 4'h1:seg_r=8'hf9; 4'h2:seg_r=8'ha4; 4'h3:seg_r=8'hb0; 4'h4:seg_r=8'h99; 4'h5:seg_r=8'h92; 4'h6:seg_r=8'h82; 4'h7:seg_r=8'hf8; 4'h8:seg_r=8'h80; 4'h9:seg_r=8'h90; 4'ha:seg_r=8'hbf; default:seg_r=8'hff; endcase endendmodule
EDA数字钟课程设计
用数字钟专用芯片lm8560,lm8361,tms3450或者用中规模集成电路390,290,248等来实现.
EDA数字钟程序
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EDA编程数字钟能进行正常的时、分、秒，小时计时要求为12进制，分和秒为60进制循环，要求整点和12点整报时
1.分秒六十进制电路模块count60的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_count60 isport(clk:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0);present:in std_logic;co:out std_logic); end wj7157_count60;architecture rtl of wj7157_count60 is signal co_1:std_logic;beginprocess(clk,present)beginif present='0' then bcd1<=0000;else if clk='1' and clk'event then if bcd1=1001 then bcd1<=0000; else bcd1<=bcd1+'1';end if; end if; end if;end process;process(clk,present,bcd1)beginif present='0' then bcd10<=0000;co_1<='0';else if clk='1' and clk'event thenif bcd1=1000 and bcd10=0101 then co_1<='1';elsif bcd1=1001 and bcd10=0101 then bcd10<=0000;co_1<='0';elsif bcd1=1001 then bcd10<=bcd10+'1';co_1<='0';end if;end if;end if;end process;co<=not co_1;end rtl;3.时十二进制电路模块count12的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_count12 isport(clk:in std_logic; bcd10,bcd1:buffer std_logic_vector(3 downto 0));end wj7157_count12;architecture rtl of wj7157_count12 is beginprocess(clk)beginif clk='1' and clk'event then if bcd10=0001 then if bcd1=0001 then bcd1<=0000;else bcd1<=bcd1+'1';end if;else if bcd1=1001 then bcd1<=0000;else bcd1<=bcd1+'1';end if;end if;end if;end process;process(clk,bcd1) beginif clk='1' and clk'event thenif bcd1=0001 and bcd10=0001 then bcd10<=0000;elsif bcd1=1001 then bcd10<=bcd10+'1';end if;end if;end process;end rtl; 时十二进制电路模块count12时序仿真波形4.动态译码及显示扫描模块Display的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity wj7157_display isport( din0，din1,din2,din3,din4,din5:in std_logic_vector(3 downto 0);clk:in std_logic;led_sa，led_sb，led_sc，led_a，led_b，led_c，led_d，led_e，led_f，led_g，led_dp:out std_logic);end wj7157_display;architecture behave of wj7157_display is signal seg: std_logic_vector(6 downto 0);signal sel: std_logic_vector(2 downto 0);signal num: std_logic_vector(3 downto 0); signal s: std_logic_vector(2 downto 0); begin led_sa<=sel(0);led_sb<=sel(1);led_sc<=sel(2);led_a<=seg(0);led_b<=seg(1);led_c<=seg(2);led_d<=seg(3);led_e<=seg(4);led_f<=seg(5);led_g<=seg(6); process(clk) begin if clk'event and clk='1' then if s=101 then s<=000; else s<=s+'1'; end if;end if;end process;process(s,din0,din1,din2,din3,din4,din5)beginif s=000 then sel<=000;num<=din4;led_dp<='0'; elsif s=001 then sel<=001;num<=din5;led_dp<='0'; elsif s=010 then sel<=010;num<=din2;led_dp<='0'; elsifs=011 then sel<=011;num<=din3;led_dp<='0'; elsif s=100 then sel<=100;num<=din0;led_dp<='0'; elsif s=101 then sel<=101;num<=din1;led_dp<='0'; else sel<=XXX;num<=XXXX;led_dp<='0';end if;end process;seg<=0111111 when num = 0 else 0000110 when num = 1 else 1011011 when num = 2 else 1001111 when num = 3 else 1100110 when num = 4 else 1101101 when num = 5 else 1111101 when num = 6 else 0000111 when num = 7 else 1111111 when num = 8 else 1101111 when num = 9 else 1110111 when num = 10 else 1111100 when num = 11 else 0111001 when num = 12 else 1011110 when num = 13 else 1111001 when num = 14 else 1110001 when num = 15 else 0000000; end behave;动态译码及显示扫描模块Display时序仿真波形5.报时电路设计模块ring的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_ring isport(clk1,clk2:in std_logic;m1,m10,s1,s10:in std_logic_vector(3 downto 0);q:out std_logic);end wj7157_ring;architecture behav of wj7157_ring isbeginprocess(m1,m10,s1,s10)begin if m10=0101 and m1=1001 thenif s10=0101 thenif s1=0101 or s1=0111 or s1=1001 then q<=clk1;end if;end if;elsif m10=0000 and m1=0000 and s10=0000 and s1=0000 then q<=clk2;elseq<='0';end if;end process;end behav; 报时电路设计模块ring时序仿真波形6.分频器电路模块div的VHDL程序（5MHz频率分频为1kHz,2kHz,5Hz）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj_div isport(clk_50MHz:in std_logic;clk_2kHz,clk_1kHz,clk_5Hz: out std_logic);end wj_div;architecture rtl of wj_div issignal q1,q2,q3 : integer range 0 to 10000100; beginprocess(clk_50MHz)beginif clk_50MHz='1' and clk_50MHz'event then if q1=24999 thenq1<=0; clk_2kHz<='1'; else q1<=q1 + 1;clk_2kHz<='0';end if;end if;end process;process(clk_50MHz)beginif clk_50MHz='1' and clk_50MHz'event then if q2=49999 then q2<=0;clk_1kHz<='1'; else q2<=q2 + 1;clk_1kHz<='0'; end if;end if;end process;process(clk_50MHz)beginif clk_50MHz='1' and clk_50MHz'event then if q3=9999999 then q3<=0;clk_5Hz<='1';else q3<=q3 + 1;clk_5Hz<='0';end if;end if;end process;end rtl;分频器电路模块div时序仿真波形因为仿真数量过大以及软件仿真条件不足等无法得出波形7.五分频电路模块div5的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_div5 is port(clk: in std_logic; q :out std_logic); end wj7157_div5; architecture rtl of wj7157_div5 is signal q1: std_logic_vector(2 downto 0); begin process(clk) begin if clk='1' and clk'event then if q1=100 then q1<=000; q<='1'; else q1<=q1 + '1';q<='0'; end if;end if;end process;end rtl; 时序仿真波形8.去抖动电路模块qudou的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_qudou is port(clk:in std_logic; din: in std_logic; dout:out std_logic); end;architecture rtl of wj7157_qudou is signal cnt: std_logic_vector(6 downto 0);beginprocess(clk) begin if clk'event and clk='1' then if din = '0' then if cnt =1100011then dout <= '0';cnt<=0000000; else cnt<=cnt+1; dout<='1'; end if; else dout<='1'; end if；end if; end process; end; 去抖动电路qudou时序仿真波形因为仿真数量过大以及软件仿真条件不足等无法得出波形9.二选一电路模块mux2的VHDL程序library ieee;use ieee.std_logic_1164.all;entity wj7157_mux2 is port(a,b:in bit; sel:in bit; q:out bit);end entity wj7157_mux2;architecture one of wj7157_mux2 is begin q<=a when sel='0' else b;end architecture one； 二选一电路模块mux2时序仿真波形10.四选二电路模块mux4的VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wj7157_mux42 is port(a,b,c,d:in std_logic_vector(3 downto 0); sel:in bit;q1,q2:out std_logic_vector(3 downto 0));end entity wj7157_mux42;architecture one of wj7157_mux42 is begin process(sel)beginif sel='0' then q1<=c;q2<=d;else q1<=a;q2<=b;end if;end process;end one;
EDA设计数字钟
书上有
请问一下，你那个eda数字钟设计程序 还在吗
功 能: 数码管显示的电子钟;------------------------------------------------------------------------------ORG0000HAJMPSTARTORG000BHAJMPTIMEORG0100HSTART:MOV30H, #00H ;半秒标志MOV31H, #00H ;状态标志,0FFH表示设置状态MOV32H, #00H ;闪烁显示控制,位为0对应的数码管 ;在调时状态下时闪烁MOV20H, #00H ;1\\\/20秒计数MOV21H, #00H ;秒计数MOV22H, #00H ;分计数MOV23H, #00H ;时计数MOVIP, #02H ;IP,IE初始化MOVIE, #82HMOVTMOD, #01H ;设定定时器工作方式MOVTL0, #0B0H ;定时器初值MOVTH0, #3CH SETBTR0 ;启动定时器0MOVSP, #40H ;重设堆栈指针MAIN:LCALLDISP ;调用显示子程序LCALLKEYPR ;调用按键处理子程序SJMPMAIN ;循环;定时器0中断处理程序TIME:PUSHACC ;保护现场PUSHPSWMOVTL0, #0B4H ;赋定时初值MOVTH0, #03CHINC20H ;1\\\/20秒计数器加1MOVA, 20HCJNEA, #10, IRET ;未到半秒,返回MOV20H, #00H MOVA, 30H ;修改半秒标志CPLAMOV30H, AJZIRETMOVA, 31H ;状态标志,为0FFH停止计时JNZIRETMOV20H, #00H ;一秒钟时间到MOVA, 21H ;秒加1INCAMOV21H, ACJNEA, #60, IRETMOV21H, #00H ;一分钟时间到MOVA, 22H ;分加1INCAMOV22H, ACJNEA, #60, IRETMOV22H, #00H ;一小时时间到MOVA, 23H ;小时加1INCAMOV23H, ACJNEA, #24, IRETMOV23H, #00H ;24小时到,小时清零IRET:POPPSW ;恢复现场 POPACCRETI ;中断返回;显示子程序 ;显示缓冲区2AH - 2FHDISP:MOVA, 21H ;处理秒 21H-->2FH,2EH MOVB, #10DIVABMOV2FH, BMOV 2EH, AMOVA, 22H ;处理分钟22H-->2CH,2DHMOVB, #10DIVABMOV2DH, BMOV2CH, AMOVA, 23H ;处理小时23H-->2AH,2BHMOVB, #10DIVABMOV2BH, BMOV2AH, AMOVDPTR, #DISPTAB ;段码表首地址MOVR0, #2AH ;缓冲区首地址MOVR6, #20H ;数码管位选择DISP1:MOVA, @R0 MOVCA, @A+DPTRMOVP2, #00HMOVB, AMOVA, 30H ;半秒标志JNZVIS1 ;半秒标志不为0,处理闪烁MOVA, BJMPVIS3 ;半秒标志为0,不处理闪烁VIS1:MOVA, BMOVB, AMOVA, R6ANLA, 32HJNZVIS2 ;当前位不闪烁MOVA, #00H ;当前位闪烁JMPVIS3VIS2:MOVA, BVIS3:MOVB, AMOVA, R6ANLA, #14H ;处理点的位置,点用来分隔时,分,秒JNZD1 ;显示点MOVA, BJMPD2 ;不显示点D1:MOVA, BORLA, #80H ;显示点D2:MOVP0, AMOVP2, R6CALLDELAY ;延时DISP2:INCR0MOVA, R6RRCAMOVR6, AJNZDISP1 ;R6不为0,继续显示MOVP2, #00HRET;按键判断程序KEYPR:SETBP3.5 ;检测S31JBP3.5, EXITKEYLCALLDISPJBP3.5, EXITKEYMOV21H, #00H ;进入设定状态MOV31H, #0FFHMOV32H, #33HKW1:LCALLDISPJNBP3.5, KW1 SETMIN:LCALLDISPSETBP3.5JBP3.5, SETMIN1LCALLDISPJBP3.5, SETMIN1KW2:LCALLDISP JNBP3.5, KW2JMPSETHR ;进入小时设定状态SETMIN1:SETBP3.6 ;设定分钟JBP3.6, SETMINLCALLDISPJBP3.6, SETMINKW3:LCALLDISPJNBP3.6, KW3MOVA, 22HINCACJNEA, #60, INCMINMOVA, #00HINCMIN:MOV22H, AJMPSETMINSETHR:MOV32H, #0FHLCALLDISPSETBP3.5JBP3.5, SETHR1LCALLDISPJBP3.5, SETHR1KW4:LCALLDISPJNBP3.5, KW4JMPEXITKEY ;退出设定状态SETHR1: SETBP3.6 ;设定小时JBP3.6, SETHRLCALLDISPJBP3.6, SETHRKW5:LCALLDISPJNBP3.6, KW5MOVA, 23HINCACJNEA, #24, INCHRMOVA, #00HINCHR:MOV23H, AJMPSETHREXITKEY:MOV31H, #00HMOV32H, #3FHRETDELAY:MOVR7, #0FFHDJNZR7, $RET;共阴数码管显示代码,最低位对应段a;0,1,2,3,4,5,6,7,8,9DISPTAB:DB 3FH, 06H, 5BH, 4FH, 66HDB 6DH, 7DH, 07H, 7FH, 6FH END
